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Dr. Yehuda Afek, afek@math.tau.ac.il
Office hours: ***, Schreiber 218 |
Dr. Nathan Intrator, nin@math.tau.ac.il
Office hours: Thursday, 10:00-12:00, Schreiber 216 |
| Lecture I: Tuesday 10-13, Shreiber 12 | Lecture II: Thursday 15-18, Ornstein 005 |
1. Nov/4 (Nathan) Algebra of logical variables
a. Logical variables and functions
b. The OR, AND, NOT functions
c. Binary, Octal and Hexadecimal number systems
a. Bases transfer of integers and fractions
b. The one's complement and two's complement
c. Representation of signed numbers
d. Boolean Algebra Theorems
e. De. Morgan's Theorem
f. The XOR, NAND and NOR functions
g. Universal System
2. Nov/11 (Nathan) Logical Functions / Basic Combinatorial Circuits
a. Standard forms for logical functions
b. Sum of products and products of sums (Minterms and Maxterms)
c. Simplification of Logical functions using Boolean Algebra Theorems
d. Simplification using Karnaugh Maps
e. Circuit implementation
f. The Don't care utility for function minimization
3. Nov/18 (Nathan) Flip-Flops Registers and Counters
a. Decoders and Encoders
b. Introduction:
The basic idea of a bus
The need for latch and synchronization
c. A latch with NAND gates
d. Clocked FF
e. Truth table and timing diagram for a FF
4. Nov/25 (Nathan) Boolean Arithmetics
a. Two phase clocking and the Master/Slave RS FF
b. The JK FF
c. Shift registers and Multiplexers.
d. Various counters
e. Half and full adders
f. Serial implementation of a full adder
g. Fast adders: the look ahead carry
5. Dec/2 (Yehuda) RISC instruction set and assembly language.
a. From programs (software) to hardware.
b. MA BA BARZELIM.
c. Integrated circuits.
d. Historical perspective.
e. Machine languages and assembly languages.
f. The MIPS R2000 Assembly language.
g. The represantation of istructions in the computer.
6. Dec/9 (Yehuda) Assembler, loader, linker.
a. Assembler.
b. Linker.
c. Loader.
7. Dec/9 - Dec/16 (Yehuda) Single cycle architecture
Building a CPU from basic components:
a. Single Cycle.
o Simple implementation.
o Control Unit - relation to istruction set.
o The problems of single-cycle.
b. Multi Cycle.
o Implementation.
o Control Unit.
o The problems with multi-cycle.
c. Micro-programming.
Another approach.
8. Dec/23 (Yehuda) The Pipelining Architecture:
a. Pipelined datapath.
b. Pipeline control.
c. Data Hazards.
9. Dec/30 (Yehuda) Pipelining (Cont) Hazard detection and resolution
a. Solutions: NOPs and Bubbles.
b. Forwarding.
c. Branch hazards.
d. Exceptions.
e. Interrupts.
10. Jan/6 (Nathan) Finite state machine, Sequential Circuits
a. Internal, external and input states
b. The state and transition diagrams
c. Moor and Mealy circuits
d. The choice
d. A sequence detector
11. Jan 13 (Nathan) Finite state machine (continued)
a. Elimination of redundant states
b. Elimination of critical races
Computer Periferials and components:
c. Types of Memories (Fast, slow, (non)volatile
d. Disk structure: access time, transfer rate
e. I/O via DMA
12. Jan 20 (Nathan)
Review and solution of exam problems
13. Jan 27 (Yehuda) Memory Hierarchies.
a. Caches.
b. Paging.
c. Virtual Memory.
Memory Organization
a. Memory technology
b. Random-access memories
c. Serial-access memories
d. Virtual memory
e. Segments, pages and files
f. High speed memories
g. Interleaved memories
h. Cache memory
14. Feb 3 (Yehuda) Advance topics in computer architecture.
a. Beyond the RISC/SICS architectures.
Overflows
Basic Combinatorial Circuits
e. The floating point system and computer accuracy
g. Multiplication and division
a. Implementation of logic gates with resistors and switches
b. The transistor
c. Families of logic circuits: TTL CMOS ECL
d. Heat dissipation: tradeoff between density and speed
e. Load capacity: Fan in and Fan out of logic circuits
f. Time race problems, the need for synchrony
System Organization
a. Communication:
Bus communication and control
Computer networks
b. Input and output systems
c. Programmed IO
d. DMA and interrupts
e. IO processors
f. Some concepts of parallel processing
Pipeline Processors
Vector processing
Multiprocessors